Field of the Invention
The present disclosure relates to a field-effect transistor, a display element, an image display device, and a system.
Description of the Related Art
Field-effect transistors (FETs) are transistors which control electric current between a source electrode and a drain electrode based on the principle that an electric field is applied to a gate electrode to provide a gate in a flow of electrons or holes utilizing an electric field of a channel.
By virtue of their characteristics, the FETs have been used as, for example, switching elements and amplifying elements. The FETs are low in gate current and have a flat structure, and thus can be easily produced and integrated as compared with bipolar transistors. For these reasons, the FETs are essential elements in integrated circuits used in the existing electronic devices. The FETs have been applied to, for example, active matrix displays as thin film transistor (TFTs).
In recent years, flat panel displays (FPDs), liquid crystal displays (LCDs), organic electroluminescent (EL) displays, and electronic paper have been put into practice.
These FPDs are driven by a driving circuit containing TFTs using amorphous silicon or polycrystalline silicon in an active layer. The FPDs have been required to have an increased size, improved definition and image quality, and an increased driving speed. To this end, there is a need for TFTs that have high carrier mobility, a high on/off ratio, small changes in properties over time, and small variation between the elements.
However, amorphous silicon or polycrystalline silicon have advantages and disadvantages. It was therefore difficult to satisfy all of the above requirements at the same time. In order to respond to these requirements, developments have been actively conducted on TFTs using, in an active layer, an oxide semiconductor the mobility of which can be expected to be higher than amorphous silicon. For example, disclosed is a TFT using InGaZnO4 in a semiconductor layer (see, for example, K. Nomura, and 5 others “Room-temperature fabrication of transparent flexible thin film transistors using amorphous oxide semiconductors”, NATURE, VOL. 432, 25, Nov., 2004, pp. 488 to 492 (hereinafter may be referred to as Non-Patent Literature 1)).
In Japanese Unexamined Patent Application Publication No. 2011-216694 (hereinafter may be referred to as Patent Literature 1), an etching stopper layer is formed on an active layer (a semiconductor layer). With this configuration, the active layer does not receive any damage upon etching for a source electrode and a drain electrode because the active layer is protected by the etching stopper layer.
In Japanese Unexamined Patent Application Publication No. 2014-041958 (hereinafter may be referred to as Patent Literature 2), an oxide semiconductor layer is used as an etching stopper in order to prevent a gate insulating layer from being etched upon patterning of a channel passivation layer.